
Set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 Set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 Set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files Set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" Set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:52:51 MARCH 03, 2014" Set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" Set_global_assignment -name TOP_LEVEL_ENTITY badprog1

Set_global_assignment -name DEVICE EP2C20F484C7 Set_global_assignment -name FAMILY "Cyclone II" qsf extension means: Quartus Settings File. You’re maybe wondering where data is saved once created with a CLI or directly from the Quartus GUI.Īctually a file with a.
#USING ALTERA QUARTUS II CODE#
Quartus_map $PROJECT -source="$ TOP_LEVEL_ENTITY" -family="$DEVICE_FAMILY"įurthermore don’t forget to add double quotes, even in the code line, otherwise it won’t work. The variable names are free, you could write yours, but don’t forget to change them also, when you call them, that is to say in the command line itself.įor example TOP_LEVEL_ENTITY must be correct when you use it with: In the file you can see variables written in uppercase. Quartus_fit $PROJECT -part="$DEVICE_PART" -pack_register="$PACKING_OPTION"Įvery command line is executed one after another.

Quartus_map $PROJECT -source="$TOP_LEVEL_ENTITY" -family="$DEVICE_FAMILY" So let's create a file named code.sh (sh = shell) and, inside, add the following code: This time, instead of typing each command at a time, we're going to create a file with all those commands inside. To remove db, you'll certainly have to close Quartus GUI first. To see that, you can remove all directories and relaunch the command. So, the compile command will create the four following directories with files inside:
#USING ALTERA QUARTUS II HOW TO#
To know how to use the flow option, type it:Ī simple quartus_sh -help we'll help you to know every option available. The -flow option allows to specifiy the command you would like to use, such as compile and the entity, in our case badprog1. Compilingįor that, open Cygwin and go until the directory where there's your project, for example mine is: With this simple easy basic code, it'll be possible to compile the project. Write down the following code within this new Verilog file and save it as badprog1.v. Then File > New > Design Files > Verilog HDL File > OK.

Select EP2C20F484C7 in the Available devices list > Next > Simulation > ModelSim-Altera > Format(s) > Verilog HDL > Next > Finish.
